1. Field of the Invention
The present invention relates to the field of computer aided design, in particular a three-dimensional solids modeling approach for simulating the manufacture of integrated circuits.
2. Description of the Related Art
The computer simulation of the manufacture of integrated circuits is commonly referred to as process simulation. Process simulation is a valuable tool in the design and manufacture of integrated circuits. It has the benefits of reducing design times and reducing experimentation and manufacturing costs. In practice, process simulation involves determining the effect of the successive deposition (i.e. depositing material), etch (i.e. removing material), lithography or other process steps on a semiconductor wafer during manufacture. Broadly speaking, process simulation can be divided into topography simulation and bulk process simulation. Topography simulation, which can be used with such process steps as deposition, etch, and lithography, is concerned mainly with the change of the geometry of the materials comprising a semiconductor wafer. Bulk process simulation, which is used with such processes as diffusion, ion implantation and oxidation, is concerned mainly with the re-distribution of the dopant impurities in the semiconductor devices. Oxidation is actually an intermediate case, affecting both the geometry and the distribution of dopant impurities.
An application of process simulation is to create computer representations of wafer structures for use by other analysis programs. Such analysis programs can then calculate properties of the device, such as electrical characteristics, thermal properties, mechanical properties, etc.
In the design of semiconductors, it is the shape and composition of the resulting structure which cause it to operate correctly. It is useful to be able to view the layers comprising a semiconductor wafer during the manufacturing process in order to identify undesirable shapes or results. For example, if a particular layer is etched too deep, e.g. it inadvertently exposes a second layer, a visual inspection can readily detect the error. This avoids the costly and time consuming alternatives of manufacturing and testing wafers. Additionally, a computer simulation provides for viewing what may only be visible with an electron microscope.
Topography simulation is complicated by the fact that various shapes result during the steps of different process technologies. FIGS. 1a-1c represent various shapes that are created at convex and concave plane interfaces. A convex plane interface is one where outer surface of the planes is greater than 180 degrees. A concave plane interface is one where the outer surface of the planes is less than 180 degrees. Referring to FIG. 1a, an original material having the shape 102 has undergone an isotropic etch process step resulting in the shape 101. Vertex points 103 and 104 of shape 102 are positioned at concave intersections between two faces. It should be noted that the faces define a 90 degree (or sharp) angle at the vertex points 103 and 104. As illustrated in shape 101, at points 105 and 106, the resulting interface at the concave interface is rounded. However, when comparing the convex intersection points 107 and 108 of shape 102 with their counterparts 109 and 110 of shape 101, it is observed that a 90 degree (sharp) edge is maintained.
FIG. 1b illustrates the effect during an isotropic deposition process step. Vertex points 125 and 126 of shape 122 are positioned at concave intersections between two faces. It should be noted that the faces define a 90 degree (or sharp) angle at the vertex points 125 and 126. As illustrated in shape 121, at points 123 and 124, the resulting interface at the concave interface retains a 90 degree (sharp) edge. However, when comparing the convex intersection points 129 and 130 with their counterparts 127 and 128, it is observed that a rounded edge is created.
Referring to FIG. 1c, the shape created as a result of a sputter etch is illustrated. In a sputter etch, the etch rate is dependent on surface orientation with respect to the direction of the trajectory of an etching particle. The etch rate will typically peak at a surface orientation ranging from 45 to 80 degrees. In any event, a sputter etch on the material having a shape 141 will result in the material having a new shape 142. Of particular interest is the fact that the faces 143 and 144 will become angled and somewhat rounded as illustrated by the faces 145 and 146. This is due to the angular dependence of the etch rates of the etching particles striking portions of surface 141, thus leading to the illustrated shape 142.
A further condition of the wafer that must be accurately simulated are voids. Voids are created during deposition process steps. Such a void is illustrated in FIG. 1d. In FIG. 1d, metal lines 150 are to be separated from a subsequent layer by an oxide deposition. The deposition may occur over successive layers, here illustrated by layers 151, 152 and 153. Between the layers 151, and 152 a void 154 has been created. It is desirable not to have voids in a wafer. For example, during fabrication it may be a source of gaseous build ups that may subsequently be released and destroy portions of the wafer.
Two-dimensional (2-D) process simulation is known in the art and is used extensively. Such prior art 2-D process simulation tools include SUPREM (available from Stanford University) and SAMPLE (available from the University of California at Berkeley). However, 2-D process simulation does not provide all desired simulation results. For example, as the miniaturization of circuits increase, 2-D process simulators do not have the capabilities to accurately predict certain features, e.g. the shape around a hole or an intersecting point of metal lines. Three-dimensional (3-D) process simulation is desirable in order to obtain more precise and complete simulation results.
Three-dimensional (3-D) process simulation tools are known in the art. One such 3-D process simulation tool is the Oyster system. The Oyster system is an internally used process simulation tool of the IBM Corporation and is described in detail in an article entitled "OYSTER: A Study of Integrated Circuits as Three-Dimensional Structures," G. M. Koppelman and M. A. Wesley, IBM Journal of Research and Development 276, No. 2, pgs 149-163 (1983). The Oyster system is based on a more general concept of solids modeling. In the Oyster system, a geometric model represents the materials comprising the topography of a wafer as solids. Changes to the topography are created using geometric operations (i.e. boolean set operations). The Oyster system is built around a general solid modeling tool that provides the basic operations and data structures for a simulation.
The Oyster system utilizes a theoretical construct of a Cumulative Translational Sweeps (CTS) for shaping geometric objects. The CTS is used in combination with boolean set operations to simulate growth and shrinking over boundary regions of geometric objects. This aspect of the Oyster System, termed the CTS method, is described in detail in the publication entitled "Shaping Geometric Objects by Cumulative Translation Sweeps", R. C. Evans, G. Koppelman, V. T. Rajan, IBM Journal of Research and Development, pgs. 343-360, Volume 31, No. 3, May 1987 and in U.S. Pat. No. 4,785,399, entitled "Shaping Geometric Objects by Cumulative Translational Sweeps".
As described above, the CTS method operates over the boundary regions of polyhedral representations of solid objects, using shaping polyhedrons (or shaping objects). A requirement in the CTS method is that a shaping polyhedron be from the polytope family of zonetopes. Generally, the CTS method provides for surface movement using the following steps:
1. Defining a set of translation vectors (which form a shaping polyhedron), which are characteristic of the desired surface movement.
2. Sweeping the original object along the first translation vector to create an intermediate solid that includes the original object. If there is only one translation vector, this becomes the new solid.
3. Sweep preceding intermediate solid along remaining translation vectors.
The CTS method sweeps the entire object at one time along the translation vector. As a result, the CTS method does not provide for simulation of process steps with spatially varying etch or deposition rates. An example of a spatially varying process step is a sputter deposition.
The use of a solid modeling approach for 3-D topography simulation is desirable since general 3-D solids modeling systems are commercially available. However, the data representations of the solids in such systems may not be ideal for creating and manipulating the structures needed for accurate and efficient topography simulation. In particular, data structures for representing adjacent materials are not commonly available.
Current techniques for the deformation of surfaces (which occurs in simulation of etch or deposition) are also not ideal. For example, a boundary representation model is often used to represent solids. Such representations become invalid when the boundaries of the solid intersect, i.e. the representation becomes self-intersecting. The representations may become invalid as they are re-formed during a process step. Such invalid representations will not allow for creation of accurate simulation results and may be unacceptable for further processing by the solids modeling system.
Several other modeling techniques for 3-D topography simulation are known in the art, namely a ray tracing model, a cell model, a network model, a diffusion model and a String model. The ray tracing model has heretofore only been used in photolithographic processing steps and is not discussed here in any detail.
The cell model is used in 3-D deposition and etch simulation. However, it has been found that the cell model does not adequately represent a curved surface. The network model is an improvement to the cell model where surface points are defined on each edge of surface tetrahedron cells. The diffusion model is also an improvement to the cell model and uses concentration contour as a surface definition. However, as with the cell model, both the network and diffusion models have been found to have difficulty in precisely treating curved surfaces as may occur during a process step.
The string model is also an approach with merit, but it often creates invalid self-intersection structures. Techniques for correcting for such self-intersecting structures have been developed, but are known to be very complex.
Another concern with any topography simulation tool is its' compatibility with other components of the process simulation environment. As described above, topography simulation is only one component of process simulation. In order to create a synergistic process simulation environment, tradeoffs should be made wherein the overall process simulation environment is improved. Such improvements may perhaps be to the detriment of one of the components of the process simulation environment.
It is an object of the present invention to provide a 3-D topography simulation tool that addresses the limitations of the CTS method. Further, it is an object of the present invention to have a solid representation created that is synergistic with other components of the process simulation environment.